ABEL®-6 Product Features

ABEL Product Information

Synario® Design Automation™'s ABEL Design Software is a powerful, Windows-based EDA solution for entering and synthesizing designs for programmable logic devices (PLDs) and complex PLDs (CPLDs). A behavioral-entry design tool, ABEL supports the ABEL Hardware Description Language (ABEL-HDL).

Advanced design features -- including full hierarchical support, an intelligent Project Navigator, and Simulation Waveform Viewer, give you unprecedented design power and flexibility. And because ABEL runs under the friendly, graphical Microsoft® Windows operating environment, it makes designing for PLDs and CPLDs easier than ever.

ABEL Project Navigator

The ABEL Project Navigator is a unique design manager that organizes your source files and presents an easy-to-follow checklist of processing steps customized for the particular device you are targeting. (Or, design with a virtual device and choose a target architecture later.) Processing options are intelligently defaulted, and detailed, and device-specific help is available on-line for each design step. With the Project Navigator, it's easy to get started and move from entry to implementation in minutes even when you're targeting a device architecture with which you're not familiar.

Behavioral Entry with Hierarchical Support

Using HDLs with hierarchical support means you can enter large, all-behavioral designs without drawing any schematics. And, the device-specific logic synthesis lets you easily migrate these designs to any other device supported by ABEL. You can also import your existing PLD designs into a larger design, add any new logic required, and then reimplement the design in a CPLD. Existing designs can be tied together behaviorally, and the whole design is guaranteed targetable to all supported architectures.

OPEN-ABEL

 To support future device growth, ABEL's architecture is open. This allows semiconductor manufacturers and other technology partners to interface and integrate their device fitters and other supporting software into the ABEL environment.

Design Entry Methods

ABEL Hardware Description Language. ABEL-HDL is a hardware description language optimized for (but not limited to) programmable integrated circuit design. It is device-independent, so you don't have to specify any device-specific parameters in your entry instead, you can focus on your design. There is no need to specify pin assignments, node assignments, or device architecture details, for example. Once the design has been entered and functionally verified, it can then be optimized with vendor-specific kits with vendor fitting/routing technology and output in a vendor-specific format or JEDEC file.

State-machine synthesis. State machines can be entered independently of device architecture and flip-flop type. ABEL will synthesize optimal circuits automatically. Both Moore and Mealy state machines are supported via IF-THEN-ELSE, CASE, and GOTO statements.

Logic-equation design entry. High-level logic equations are supported, incorporating Boolean operators (NOT, AND, OR, XOR), arithmetic operators (SUBTRACTION, ADDITION, MULTIPLICATION, DIVISION, SHIFT LEFT, SHIFT RIGHT), relational operators (LESS THAN, GREATER THAN, COMPARISON), and assignment operators (EQUALS).

Truth-table design entry. Truth tables are used to specify input-to-output relationships for modules like decoders. On-set, off-set, and don't-care conditions, as well as expressions (not just constants), can be specified.

Extensive on-line help. You can easily access ABEL's extensive on-line help with just one keystroke. The context-sensitive help provides information that is specific to the item on which the cursor resides, be it a menu item, a dialog box, or a keyword within your design file. In addition, fully indexed and categorized help is available, including a list of commented design examples and device architecture information.

Design Verification Features

Design simulation. Functional simulation can be performed immediately after design entry, independently of the target device. There is no need to perform optimization before simulation.

PLD device simulation. After logic synthesis and device selection are performed, designs targeted for PLDs can also be functionally simulated at the device level (JEDEC file simulation). As a result, designs can be fully verified before a device is ever programmed. This also verifies that the design properly fits into the device, that the JEDEC file is correct, and that no errors were introduced during the synthesis process.

A friendly simulation environment. Simulation results are presented in a waveform viewer display that has the familiar look of a logic analyzer. With it you can add, delete, or move displayed signals. The viewer updates whenever you simulate, even after each step of a single-step session. Report files indicate where errors occurred during simulation, and a double click on a specific error message causes the waveform viewer to jump to the cycle automatically.

Optimization/Synthesis Features

Automatic logic optimization. ABEL uses state-of-the-art logic synthesis technology to fit designs into silicon, and supports multiple strategies of logic reduction. The algorithms include device-independent synthesis techniques, as well as device-specific fitters that understand how to efficiently utilize the most complex features of today's newest PLDs and CPLDs.

Don't-care conditions supported. ABEL intelligently takes into account don't-care conditions (such as unspecified state transitions) used in your design. These are used to reduce the logic required to implement your design, and can result in significant silicon savings.

Flip-Flop Transformation. ABEL offers flip-flop transformation (FFT), which supports register and combinatorial logic transformations, as well as general normalizations to a design to target the design for different device technologies.

Node Collapsing. ABEL supports Node Collapsing for a more efficient reduction, optimization, and synthesis process.

Vendor Kits and fitting/routing. To guarantee efficient use of silicon, Synario Design Automation provides vendor-specific interface kits for unique programmable architectures. Because no single synthesis algorithm can be used for all types of devices, interface kits to vendor-specific fitting and routing software is necessary to take advantage of complex device features like buried nodes, expander arrays, and multiple flip-flop types.

Each kit combined with a vendor-specific fitter is capable of automatically taking your design and fitting it into a unique device-architecture class. Pin assignment and output macrocell configuration are automatically performed, allowing you to work on the details of your design, not the device. You can manually override any of the fitter features, of course, to customize the fit to your needs.

The intelligent Device Fitter technology also lets you quickly and easily target a single device-independent design in numerous PLDs, and benchmark the results by comparing report files. Reports on device utilization and operating frequency are generated by each specific fitter run on any given design, giving you significant benchmarking capabilities prior to ever buying a device.

Output Format Features

ABEL automatically creates standard JEDEC programmer load files for PLDs and CPLDs. These files can be easily downloaded to a PLD programmer for device programming and testing.

User Documentation

User manual. The ABEL user manual includes chapters on behavioral entry for programmable devices, ABEL-HDL, understanding ABEL, and detailed design considerations for all of the major vendors' devices.

Tutorials. Multiple tutorials are included to get you started with ABEL quickly.

Design examples. Over 100 design examples are included with ABEL. These examples show the use of equations, state diagrams, and truth tables while giving you a feel for typical design applications.



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